mirror of
https://github.com/verilator/verilator.git
synced 2025-01-12 01:27:36 +00:00
5 lines
292 B
Plaintext
5 lines
292 B
Plaintext
%Warning-WIDTH: t/t_flag_wfatal.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
|
wire [3:0] foo = 6'h2e;
|
|
^
|
|
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|