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797 lines
29 KiB
C++
797 lines
29 KiB
C++
//*************************************************************************
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// DESCRIPTION: Verilator: Gate optimizations, such as wire elimination
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//
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// Code available from: http://www.veripool.org/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2003-2011 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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// V3Gate's Transformations:
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//
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// Extract a graph of the *entire* netlist with cells expanded
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// Perform constant optimization across the graph
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// Create VARSCOPEs for any variables we can rip out
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include <cstdio>
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#include <cstdarg>
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#include <unistd.h>
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#include <algorithm>
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#include <iomanip>
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#include <vector>
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#include <list>
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#include "V3Global.h"
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#include "V3Gate.h"
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#include "V3Ast.h"
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#include "V3Graph.h"
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#include "V3Const.h"
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#include "V3Stats.h"
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typedef list<AstNodeVarRef*> GateVarRefList;
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//######################################################################
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class GateBaseVisitor : public AstNVisitor {
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public:
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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};
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//######################################################################
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// Support classes
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class GateEitherVertex : public V3GraphVertex {
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AstScope* m_scopep;
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bool m_reducible; // True if this node should be able to be eliminated
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bool m_consumed; // Output goes to something meaningful
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public:
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GateEitherVertex(V3Graph* graphp, AstScope* scopep)
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: V3GraphVertex(graphp), m_scopep(scopep), m_reducible(true), m_consumed(false) {}
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virtual ~GateEitherVertex() {}
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// Accessors
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virtual string dotStyle() const { return m_consumed?"":"dotted"; }
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AstScope* scopep() const { return m_scopep; }
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bool reducible() const { return m_reducible; }
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void setConsumed(const char* consumedReason) {
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m_consumed = true;
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//UINFO(0,"\t\tSetConsumed "<<consumedReason<<" "<<this<<endl);
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}
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bool consumed() const { return m_consumed; }
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void clearReducible(const char* nonReducibleReason) {
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m_reducible = false;
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//UINFO(0," NR: "<<nonReducibleReason<<" "<<name()<<endl);
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}
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};
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class GateVarVertex : public GateEitherVertex {
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AstVarScope* m_varScp;
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bool m_isTop;
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bool m_isClock;
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AstNode* m_rstSyncNodep; // Used as reset and not in SenItem, in clocked always
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AstNode* m_rstAsyncNodep; // Used as reset and in SenItem, in clocked always
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public:
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GateVarVertex(V3Graph* graphp, AstScope* scopep, AstVarScope* varScp)
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: GateEitherVertex(graphp, scopep), m_varScp(varScp), m_isTop(false)
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, m_isClock(false), m_rstSyncNodep(NULL), m_rstAsyncNodep(NULL) {}
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virtual ~GateVarVertex() {}
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// Accessors
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AstVarScope* varScp() const { return m_varScp; }
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virtual string name() const { return (cvtToStr((void*)m_varScp)+" "+varScp()->name()); }
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virtual string dotColor() const { return "blue"; }
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bool isTop() const { return m_isTop; }
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void setIsTop() { m_isTop = true; }
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bool isClock() const { return m_isClock; }
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void setIsClock() { m_isClock = true; setConsumed("isclk"); }
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AstNode* rstSyncNodep() const { return m_rstSyncNodep; }
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void rstSyncNodep(AstNode* nodep) { m_rstSyncNodep=nodep; }
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AstNode* rstAsyncNodep() const { return m_rstAsyncNodep; }
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void rstAsyncNodep(AstNode* nodep) { m_rstAsyncNodep=nodep; }
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};
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class GateLogicVertex : public GateEitherVertex {
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AstNode* m_nodep;
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AstActive* m_activep; // Under what active; NULL is ok (under cfunc or such)
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bool m_slow; // In slow block
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public:
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GateLogicVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep, AstActive* activep, bool slow)
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: GateEitherVertex(graphp,scopep), m_nodep(nodep), m_activep(activep), m_slow(slow) {}
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virtual ~GateLogicVertex() {}
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// Accessors
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virtual string name() const { return (cvtToStr((void*)m_nodep)+"@"+scopep()->prettyName()); }
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virtual string dotColor() const { return "yellow"; }
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AstNode* nodep() const { return m_nodep; }
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AstActive* activep() const { return m_activep; }
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bool slow() const { return m_slow; }
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};
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//######################################################################
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// Is this a simple math expression with a single input and single output?
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class GateOkVisitor : public GateBaseVisitor {
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private:
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// RETURN STATE
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bool m_isSimple; // Set false when we know it isn't simple
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GateVarRefList m_rhsVarRefs; // VarRefs on rhs of assignment
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AstNode* m_substTreep; // What to replace the variable with
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// STATE
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bool m_buffersOnly; // Set when we only allow simple buffering, no equations (for clocks)
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AstNodeVarRef* m_lhsVarRef; // VarRef on lhs of assignment (what we're replacing)
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// METHODS
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void clearSimple(const char* because) {
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if (m_isSimple) {
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m_isSimple = false;
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UINFO(9, "Clear simple "<<because<<endl);
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}
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}
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// VISITORS
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virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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// We only allow a LHS ref for the var being set, and a RHS ref for something else being read.
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if (nodep->varScopep()->varp()->isSc()) {
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clearSimple("SystemC sig"); // Don't want to eliminate the VL_ASSIGN_SI's
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}
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if (nodep->lvalue()) {
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if (m_lhsVarRef) clearSimple(">1 lhs varRefs");
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m_lhsVarRef = nodep;
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} else {
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if (m_rhsVarRefs.size()>1) {
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AstNodeVarRef* lastRefp = m_rhsVarRefs.back();
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if (0) { // Diable the multiple-input optimization
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clearSimple(">1 rhs varRefs");
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} else {
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if (m_buffersOnly) clearSimple(">1 rhs varRefs");
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if (!nodep->varScopep()->varp()->gateMultiInputOptimizable()
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// We didn't check multiInput on the first varref, so check it here
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|| !lastRefp->varScopep()->varp()->gateMultiInputOptimizable()) {
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clearSimple("!gateMultiInputOptimizable");
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}
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}
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}
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m_rhsVarRefs.push_back(nodep);
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}
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}
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virtual void visit(AstNodeAssign* nodep, AstNUser*) {
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m_substTreep = nodep->rhsp();
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if (!nodep->lhsp()->castNodeVarRef())
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clearSimple("ASSIGN(non VARREF)");
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else nodep->iterateChildren(*this);
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// We don't push logic other then assignments/NOTs into SenItems
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// This avoids a mess in computing what exactly a POSEDGE is
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// V3Const cleans up any NOTs by flipping the edges for us
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if (m_buffersOnly
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&& !(nodep->rhsp()->castVarRef()
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// Until NEW_ORDERING, avoid making non-clocked logic into clocked,
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// as it slows down the verilator_sim_benchmark
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|| (nodep->rhsp()->castNot()
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&& nodep->rhsp()->castNot()->lhsp()->castVarRef()
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&& nodep->rhsp()->castNot()->lhsp()->castVarRef()->varp()->isUsedClock())
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)) {
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clearSimple("Not a buffer (goes to a clock)");
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}
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}
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//--------------------
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// Default
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virtual void visit(AstNode* nodep, AstNUser*) {
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// *** Special iterator
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if (!m_isSimple) return; // Fastpath
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if (!nodep->isGateOptimizable()
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|| !nodep->isSplittable()) {
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UINFO(5, "Non optimizable type: "<<nodep<<endl);
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clearSimple("Non optimizable type");
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}
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else nodep->iterateChildren(*this);
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}
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public:
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// CONSTUCTORS
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GateOkVisitor(AstNode* nodep, bool buffersOnly) {
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m_isSimple = true;
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m_substTreep = NULL;
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m_buffersOnly = buffersOnly;
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m_lhsVarRef = NULL;
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// Iterate
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nodep->accept(*this);
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// Check results
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if (!m_substTreep) {
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clearSimple("No assignment found\n");
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}
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for (GateVarRefList::const_iterator it = rhsVarRefs().begin();
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it != rhsVarRefs().end(); ++it) {
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if (m_lhsVarRef && m_lhsVarRef->varScopep() == (*it)->varScopep()) {
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clearSimple("Circular logic\n"); // Oh my, we'll get a UNOPTFLAT much later.
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}
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}
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if (debug()>=9 && !m_isSimple) {
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nodep->dumpTree(cout,"\tgate!Ok: ");
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}
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}
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virtual ~GateOkVisitor() {}
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// PUBLIC METHODS
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bool isSimple() const { return m_isSimple; }
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AstNode* substTree() const { return m_substTreep; }
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const GateVarRefList& rhsVarRefs() const {
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return m_rhsVarRefs;
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}
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};
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//######################################################################
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// Gate class functions
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class GateVisitor : public GateBaseVisitor {
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private:
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// NODE STATE
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//Entire netlist:
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// AstVarScope::user1p -> GateVarVertex* for usage var, 0=not set yet
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// {statement}Node::user1p -> GateLogicVertex* for this statement
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// AstVarScope::user2 -> bool: Signal used in SenItem in *this* always statement
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// AstVar::user2 -> bool: Warned about SYNCASYNCNET
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AstUser1InUse m_inuser1;
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AstUser2InUse m_inuser2;
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// STATE
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V3Graph m_graph; // Scoreboard of var usages/dependencies
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GateLogicVertex* m_logicVertexp; // Current statement being tracked, NULL=ignored
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AstScope* m_scopep; // Current scope being processed
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AstNodeModule* m_modp; // Current module
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AstActive* m_activep; // Current active
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bool m_activeReducible; // Is activation block reducible?
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bool m_inSenItem; // Underneath AstSenItem; any varrefs are clocks
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bool m_inSlow; // Inside a slow structure
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V3Double0 m_statSigs; // Statistic tracking
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V3Double0 m_statRefs; // Statistic tracking
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// METHODS
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void iterateNewStmt(AstNode* nodep, const char* nonReducibleReason, const char* consumeReason) {
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if (m_scopep) {
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UINFO(4," STMT "<<nodep<<endl);
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// m_activep is null under AstCFunc's, that's ok.
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m_logicVertexp = new GateLogicVertex(&m_graph, m_scopep, nodep, m_activep, m_inSlow);
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if (!m_activeReducible) nonReducibleReason="Block Unreducible";
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if (nonReducibleReason) {
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m_logicVertexp->clearReducible(nonReducibleReason);
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}
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if (consumeReason) m_logicVertexp->setConsumed(consumeReason);
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if (nodep->castSenItem()) m_logicVertexp->setConsumed("senItem");
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nodep->iterateChildren(*this);
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m_logicVertexp = NULL;
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}
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}
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GateVarVertex* makeVarVertex(AstVarScope* varscp) {
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GateVarVertex* vertexp = (GateVarVertex*)(varscp->user1p());
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if (!vertexp) {
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UINFO(6,"New vertex "<<varscp<<endl);
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vertexp = new GateVarVertex(&m_graph, m_scopep, varscp);
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varscp->user1p(vertexp);
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if (varscp->varp()->isSigPublic()) {
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// Public signals shouldn't be changed, pli code might be messing with them
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vertexp->clearReducible("SigPublic");
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vertexp->setConsumed("SigPublic");
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}
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if (varscp->varp()->isIO() && varscp->scopep()->isTop()) {
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// We may need to convert to/from sysc/reg sigs
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vertexp->setIsTop();
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vertexp->clearReducible("isTop");
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vertexp->setConsumed("isTop");
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}
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if (varscp->varp()->isUsedClock()) vertexp->setConsumed("clock");
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}
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return vertexp;
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}
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void optimizeSignals(bool allowMultiIn);
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void optimizeElimVar(AstVarScope* varscp, AstNode* logicp, AstNode* consumerp);
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void warnSignals();
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void consumedMark();
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void consumedMarkRecurse(GateEitherVertex* vertexp);
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void consumedMove();
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void replaceAssigns();
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// VISITORS
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virtual void visit(AstNetlist* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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//if (debug()>6) m_graph.dump();
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if (debug()>6) m_graph.dumpDotFilePrefixed("gate_pre");
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m_graph.removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue);
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m_graph.dumpDotFilePrefixed("gate_simp");
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// Find gate interconnect and optimize
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m_graph.userClearVertices(); // vertex->user(): bool. True indicates we've set it as consumed
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// Get rid of buffers first,
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optimizeSignals(false);
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// Then propagate more complicated equations
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optimizeSignals(true);
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// Warn
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warnSignals();
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consumedMark();
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m_graph.dumpDotFilePrefixed("gate_opt");
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// Rewrite assignments
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consumedMove();
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replaceAssigns();
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}
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virtual void visit(AstNodeModule* nodep, AstNUser*) {
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m_modp = nodep;
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m_activeReducible = true;
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nodep->iterateChildren(*this);
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m_modp = NULL;
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}
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virtual void visit(AstScope* nodep, AstNUser*) {
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UINFO(4," SCOPE "<<nodep<<endl);
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m_scopep = nodep;
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m_logicVertexp = NULL;
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nodep->iterateChildren(*this);
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m_scopep = NULL;
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}
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virtual void visit(AstActive* nodep, AstNUser*) {
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// Create required blocks and add to module
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UINFO(4," BLOCK "<<nodep<<endl);
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m_activeReducible = !(nodep->hasClocked()); // Seq logic outputs aren't reducible
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m_activep = nodep;
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AstNode::user2ClearTree();
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nodep->iterateChildren(*this);
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AstNode::user2ClearTree();
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m_activep = NULL;
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m_activeReducible = true;
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}
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virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
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if (m_scopep) {
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if (!m_logicVertexp) nodep->v3fatalSrc("Var ref not under a logic block\n");
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AstVarScope* varscp = nodep->varScopep();
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if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
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GateVarVertex* vvertexp = makeVarVertex(varscp);
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UINFO(5," VARREF to "<<varscp<<endl);
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if (m_inSenItem) vvertexp->setIsClock();
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// For SYNCASYNCNET
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if (m_inSenItem) varscp->user2(true);
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else if (m_activep && m_activep->hasClocked() && !nodep->lvalue()) {
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if (varscp->user2()) {
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if (!vvertexp->rstSyncNodep()) vvertexp->rstSyncNodep(nodep);
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} else {
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if (!vvertexp->rstAsyncNodep()) vvertexp->rstAsyncNodep(nodep);
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}
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}
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// We use weight of one; if we ref the var more than once, when we simplify,
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// the weight will increase
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if (nodep->lvalue()) {
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new V3GraphEdge(&m_graph, m_logicVertexp, vvertexp, 1);
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} else {
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new V3GraphEdge(&m_graph, vvertexp, m_logicVertexp, 1);
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}
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}
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}
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virtual void visit(AstAlways* nodep, AstNUser*) {
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iterateNewStmt(nodep, (nodep->isJustOneBodyStmt()?NULL:"Multiple Stmts"), NULL);
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}
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virtual void visit(AstAlwaysPublic* nodep, AstNUser*) {
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bool lastslow = m_inSlow;
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m_inSlow = true;
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iterateNewStmt(nodep, "AlwaysPublic", NULL);
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m_inSlow = lastslow;
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}
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virtual void visit(AstCFunc* nodep, AstNUser*) {
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iterateNewStmt(nodep, "User C Function", "User C Function");
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}
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virtual void visit(AstSenItem* nodep, AstNUser*) {
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// Note we look at only AstSenItems, not AstSenGate's
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// The gating term of a AstSenGate is normal logic
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m_inSenItem = true;
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if (m_logicVertexp) { // Already under logic; presumably a SenGate
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nodep->iterateChildren(*this);
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} else { // Standalone item, probably right under a SenTree
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iterateNewStmt(nodep, NULL, NULL);
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}
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m_inSenItem = false;
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}
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virtual void visit(AstSenGate* nodep, AstNUser*) {
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// First handle the clock part will be handled in a minute by visit AstSenItem
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// The logic gating term is delt with as logic
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iterateNewStmt(nodep, "Clock gater", "Clock gater");
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}
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virtual void visit(AstInitial* nodep, AstNUser*) {
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bool lastslow = m_inSlow;
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m_inSlow = true;
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iterateNewStmt(nodep, (nodep->isJustOneBodyStmt()?NULL:"Multiple Stmts"), NULL);
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m_inSlow = lastslow;
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}
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virtual void visit(AstAssignAlias* nodep, AstNUser*) {
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iterateNewStmt(nodep, NULL, NULL);
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}
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virtual void visit(AstAssignW* nodep, AstNUser*) {
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iterateNewStmt(nodep, NULL, NULL);
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}
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virtual void visit(AstCoverToggle* nodep, AstNUser*) {
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iterateNewStmt(nodep, "CoverToggle", "CoverToggle");
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}
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virtual void visit(AstTraceInc* nodep, AstNUser*) {
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bool lastslow = m_inSlow;
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m_inSlow = true;
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iterateNewStmt(nodep, "Tracing", "Tracing");
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m_inSlow = lastslow;
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}
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virtual void visit(AstConcat* nodep, AstNUser*) {
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if (nodep->backp()->castNodeAssign() && nodep->backp()->castNodeAssign()->lhsp()==nodep) {
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nodep->v3fatalSrc("Concat on LHS of assignment; V3Const should have deleted it\n");
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}
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nodep->iterateChildren(*this);
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}
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//--------------------
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// Default
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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if (nodep->isOutputter() && m_logicVertexp) m_logicVertexp->setConsumed("outputter");
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}
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public:
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// CONSTUCTORS
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GateVisitor(AstNode* nodep) {
|
||
m_logicVertexp = NULL;
|
||
m_scopep = NULL;
|
||
m_modp = NULL;
|
||
m_activep = NULL;
|
||
m_activeReducible = true;
|
||
m_inSenItem = false;
|
||
m_inSlow = false;
|
||
nodep->accept(*this);
|
||
}
|
||
virtual ~GateVisitor() {
|
||
V3Stats::addStat("Optimizations, Gate sigs deleted", m_statSigs);
|
||
V3Stats::addStat("Optimizations, Gate inputs replaced", m_statRefs);
|
||
}
|
||
};
|
||
|
||
//----------------------------------------------------------------------
|
||
|
||
void GateVisitor::optimizeSignals(bool allowMultiIn) {
|
||
for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
|
||
if (GateVarVertex* vvertexp = dynamic_cast<GateVarVertex*>(itp)) {
|
||
if (vvertexp->inEmpty()) {
|
||
vvertexp->clearReducible("inEmpty"); // Can't deal with no sources
|
||
if (!vvertexp->isTop() // Ok if top inputs are driverless
|
||
&& !vvertexp->varScp()->varp()->valuep()
|
||
&& !vvertexp->varScp()->varp()->isSigPublic()) {
|
||
UINFO(4, "No drivers "<<vvertexp->varScp()<<endl);
|
||
if (0) {
|
||
// If we warned here after constant propagation, what the user considered
|
||
// reasonable logic may have disappeared. Issuing a warning would
|
||
// thus be confusing. V3Undriven now handles this.
|
||
vvertexp->varScp()->varp()->v3warn(UNDRIVEN,"Signal has no drivers "
|
||
<<vvertexp->scopep()->prettyName()<<"."
|
||
<<vvertexp->varScp()->varp()->prettyName());
|
||
}
|
||
}
|
||
}
|
||
else if (!vvertexp->inSize1()) {
|
||
vvertexp->clearReducible("size!1"); // Can't deal with more than one src
|
||
}
|
||
// Reduce it?
|
||
if (!vvertexp->reducible()) {
|
||
UINFO(8, "SigNotRed "<<vvertexp->name()<<endl);
|
||
} else {
|
||
UINFO(8, "Sig "<<vvertexp->name()<<endl);
|
||
GateLogicVertex* logicVertexp = dynamic_cast<GateLogicVertex*>
|
||
(vvertexp->inBeginp()->fromp());
|
||
UINFO(8, " From "<<logicVertexp->name()<<endl);
|
||
AstNode* logicp = logicVertexp->nodep();
|
||
if (logicVertexp->reducible()) {
|
||
// Can we eliminate?
|
||
GateOkVisitor okVisitor(logicp, vvertexp->isClock());
|
||
bool multiInputs = okVisitor.rhsVarRefs().size() > 1;
|
||
// Was it ok?
|
||
bool doit = okVisitor.isSimple();
|
||
if (doit && multiInputs) {
|
||
if (!allowMultiIn) doit = false;
|
||
// Doit if one input, or not used, or used only once, ignoring traces
|
||
int n=0;
|
||
for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep; edgep = edgep->outNextp()) {
|
||
GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
|
||
if (!consumeVertexp->slow()) { // Not tracing or other slow path junk
|
||
if (edgep->top()->outBeginp()) { // Destination is itself used
|
||
n += edgep->weight();
|
||
}
|
||
}
|
||
if (n>1) {
|
||
doit = false;
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
// Process it
|
||
if (!doit) {
|
||
if (allowMultiIn && (debug()>=9)) {
|
||
UINFO(9, "Not ok simp"<<okVisitor.isSimple()<<" mi"<<multiInputs
|
||
<<" ob"<<vvertexp->outBeginp()<<" on"<<(vvertexp->outBeginp()?vvertexp->outBeginp()->outNextp():0)
|
||
<<" "<<vvertexp->name()
|
||
<<endl);
|
||
for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep; edgep = edgep->outNextp()) {
|
||
GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
|
||
UINFO(9, " edge "<<edgep<<" to: "<<consumeVertexp->nodep()<<endl);
|
||
}
|
||
for (V3GraphEdge* edgep = vvertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
|
||
GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->fromp());
|
||
UINFO(9, " edge "<<edgep<<" from: "<<consumeVertexp->nodep()<<endl);
|
||
}
|
||
}
|
||
}
|
||
else {
|
||
AstNode* substp = okVisitor.substTree();
|
||
if (debug()>=5) logicp->dumpTree(cout,"\telimVar: ");
|
||
if (debug()>=5) substp->dumpTree(cout,"\t subst: ");
|
||
m_statSigs++;
|
||
while (V3GraphEdge* edgep = vvertexp->outBeginp()) {
|
||
GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
|
||
AstNode* consumerp = consumeVertexp->nodep();
|
||
optimizeElimVar(vvertexp->varScp(), substp, consumerp);
|
||
// If the new replacement referred to a signal,
|
||
// Correct the graph to point to this new generating variable
|
||
for (GateVarRefList::const_iterator it = okVisitor.rhsVarRefs().begin();
|
||
it != okVisitor.rhsVarRefs().end(); ++it) {
|
||
AstVarScope* newvarscp = (*it)->varScopep();
|
||
UINFO(9," Point-to-new vertex "<<newvarscp<<endl);
|
||
GateVarVertex* varvertexp = makeVarVertex(newvarscp);
|
||
new V3GraphEdge(&m_graph, varvertexp, consumeVertexp, 1);
|
||
newvarscp->varp()->propagateAttrFrom(vvertexp->varScp()->varp());
|
||
if (vvertexp->isClock()) {
|
||
// Propagate clock attribute onto generating node
|
||
newvarscp->varp()->usedClock(true);
|
||
varvertexp->setIsClock();
|
||
}
|
||
}
|
||
// Remove the edge
|
||
edgep->unlinkDelete(); edgep=NULL;
|
||
m_statRefs++;
|
||
}
|
||
// Remove input links
|
||
while (V3GraphEdge* edgep = vvertexp->inBeginp()) {
|
||
edgep->unlinkDelete(); edgep=NULL;
|
||
}
|
||
// Clone tree so we remember it for tracing, and keep the pointer
|
||
// to the "ALWAYS" part of the tree as part of this statement
|
||
// That way if a later signal optimization that retained a pointer to the always
|
||
// can optimize it further
|
||
logicp->unlinkFrBack();
|
||
vvertexp->varScp()->valuep(logicp);
|
||
logicp = NULL;
|
||
// Mark the vertex so we don't mark it as being unconsumed in the next step
|
||
vvertexp->user(true);
|
||
logicVertexp->user(true);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
void GateVisitor::replaceAssigns() {
|
||
for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
|
||
if (GateVarVertex* vvertexp = dynamic_cast<GateVarVertex*>(itp)) {
|
||
// Take the Comments/assigns that were moved to the VarScope and change them to a
|
||
// simple value assignment
|
||
AstVarScope* vscp = vvertexp->varScp();
|
||
if (vscp->valuep() && !vscp->valuep()->castNodeMath()) {
|
||
//if (debug()>9) vscp->dumpTree(cout, "-vscPre: ");
|
||
while (AstNode* delp=vscp->valuep()->castComment()) {
|
||
delp->unlinkFrBack()->deleteTree(); delp=NULL;
|
||
}
|
||
if (AstInitial* delp=vscp->valuep()->castInitial()) {
|
||
AstNode* bodyp=delp->bodysp();
|
||
bodyp->unlinkFrBackWithNext();
|
||
delp->replaceWith(bodyp);
|
||
delp->deleteTree(); delp=NULL;
|
||
}
|
||
if (AstAlways* delp=vscp->valuep()->castAlways()) {
|
||
AstNode* bodyp=delp->bodysp();
|
||
bodyp->unlinkFrBackWithNext();
|
||
delp->replaceWith(bodyp);
|
||
delp->deleteTree(); delp=NULL;
|
||
}
|
||
if (AstNodeAssign* delp=vscp->valuep()->castNodeAssign()) {
|
||
AstNode* rhsp=delp->rhsp();
|
||
rhsp->unlinkFrBack();
|
||
delp->replaceWith(rhsp);
|
||
delp->deleteTree(); delp=NULL;
|
||
}
|
||
//if (debug()>9) {vscp->dumpTree(cout, "-vscDone: "); cout<<endl;}
|
||
if (!vscp->valuep()->castNodeMath()
|
||
|| vscp->valuep()->nextp()) {
|
||
vscp->dumpTree(cerr, "vscStrange: ");
|
||
vscp->v3fatalSrc("Value of varscope not mathematical\n");
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
//----------------------------------------------------------------------
|
||
|
||
void GateVisitor::consumedMark() {
|
||
// Propagate consumed signals backwards to all producers into a consumed node
|
||
m_graph.userClearVertices();
|
||
for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
|
||
GateEitherVertex* evertexp = (GateEitherVertex*)vertexp;
|
||
if (!evertexp->user() && evertexp->consumed()) {
|
||
consumedMarkRecurse(evertexp);
|
||
}
|
||
}
|
||
}
|
||
|
||
void GateVisitor::consumedMarkRecurse(GateEitherVertex* vertexp) {
|
||
if (vertexp->user()) return; // Already marked
|
||
vertexp->user(true);
|
||
if (!vertexp->consumed()) vertexp->setConsumed("propagated");
|
||
// Walk sources and mark them too
|
||
for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
|
||
GateEitherVertex* eFromVertexp = (GateEitherVertex*)edgep->fromp();
|
||
consumedMarkRecurse(eFromVertexp);
|
||
}
|
||
}
|
||
|
||
void GateVisitor::consumedMove() {
|
||
// Remove unused logic (logic that doesn't hit a combo block or a display statement)
|
||
// We need the "usually" block logic to do a better job at this
|
||
for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
|
||
if (GateVarVertex* vvertexp = dynamic_cast<GateVarVertex*>(vertexp)) {
|
||
if (!vvertexp->consumed() && !vvertexp->user()) {
|
||
UINFO(8, "Unconsumed "<<vvertexp->varScp()<<endl);
|
||
}
|
||
}
|
||
if (GateLogicVertex* lvertexp = dynamic_cast<GateLogicVertex*>(vertexp)) {
|
||
AstNode* nodep = lvertexp->nodep();
|
||
AstActive* oldactp = lvertexp->activep(); // NULL under cfunc
|
||
if (!lvertexp->consumed() && oldactp) {
|
||
// Eventually: Move the statement to a new active block with "tracing-on" sensitivity
|
||
UINFO(8," Remove unconsumed "<<nodep<<endl);
|
||
nodep->unlinkFrBack();
|
||
pushDeletep(nodep); nodep=NULL;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
//----------------------------------------------------------------------
|
||
|
||
void GateVisitor::warnSignals() {
|
||
AstNode::user2ClearTree();
|
||
for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
|
||
if (GateVarVertex* vvertexp = dynamic_cast<GateVarVertex*>(itp)) {
|
||
AstVarScope* vscp = vvertexp->varScp();
|
||
AstNode* sp = vvertexp->rstSyncNodep();
|
||
AstNode* ap = vvertexp->rstAsyncNodep();
|
||
if (ap && sp && !vscp->varp()->user2()) {
|
||
// This is somewhat wrong, as marking one flop as ok for sync
|
||
// may mean a different flop now fails. However it's a pain to
|
||
// then report a warning in a new place - we should report them all at once.
|
||
// Instead we'll disable if any disabled
|
||
if (!vscp->fileline()->warnIsOff(V3ErrorCode::SYNCASYNCNET)
|
||
&& !ap->fileline()->warnIsOff(V3ErrorCode::SYNCASYNCNET)
|
||
&& !sp->fileline()->warnIsOff(V3ErrorCode::SYNCASYNCNET)
|
||
) {
|
||
vscp->varp()->user2(true); // Warn only once per signal
|
||
vscp->v3warn(SYNCASYNCNET,"Signal flopped as both synchronous and async: "<<vscp->prettyName());
|
||
ap->v3warn(SYNCASYNCNET,"... Location of async usage");
|
||
sp->v3warn(SYNCASYNCNET,"... Location of sync usage");
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
//######################################################################
|
||
// Push constant into expressions and reevaluate
|
||
|
||
class GateElimVisitor : public GateBaseVisitor {
|
||
private:
|
||
// NODE STATE
|
||
// STATE
|
||
AstVarScope* m_elimVarScp; // Variable being eliminated
|
||
AstNode* m_replaceTreep; // What to replace the variable with
|
||
bool m_didReplace; // Did we do any replacements
|
||
// VISITORS
|
||
virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
|
||
if (nodep->varScopep() == m_elimVarScp) {
|
||
// Substitute in the new tree
|
||
// It's possible we substitute into something that will be reduced more later
|
||
// however, as we never delete the top Always/initial statement, all should be well.
|
||
m_didReplace = true;
|
||
if (nodep->lvalue()) nodep->v3fatalSrc("Can't replace lvalue assignments with const var");
|
||
AstNode* substp = m_replaceTreep->cloneTree(false);
|
||
if (nodep->castNodeVarRef()
|
||
&& substp->castNodeVarRef()
|
||
&& nodep->same(substp)) {
|
||
// Prevent a infinite loop...
|
||
substp->v3fatalSrc("Replacing node with itself; perhaps circular logic?");
|
||
}
|
||
// Which fileline() to use?
|
||
// If replacing with logic, an error/warning is likely to want to point to the logic
|
||
// IE what we're replacing with.
|
||
// However a VARREF should point to the original as it's otherwise confusing
|
||
// to throw warnings that point to a PIN rather than where the pin us used.
|
||
if (substp->castVarRef()) substp->fileline(nodep->fileline());
|
||
nodep->replaceWith(substp);
|
||
nodep->deleteTree(); nodep=NULL;
|
||
}
|
||
}
|
||
virtual void visit(AstNode* nodep, AstNUser*) {
|
||
nodep->iterateChildren(*this);
|
||
}
|
||
public:
|
||
// CONSTUCTORS
|
||
virtual ~GateElimVisitor() {}
|
||
GateElimVisitor(AstNode* nodep, AstVarScope* varscp, AstNode* replaceTreep) {
|
||
m_didReplace = false;
|
||
m_elimVarScp = varscp;
|
||
m_replaceTreep = replaceTreep;
|
||
nodep->accept(*this);
|
||
}
|
||
bool didReplace() const { return m_didReplace; }
|
||
};
|
||
|
||
void GateVisitor::optimizeElimVar(AstVarScope* varscp, AstNode* substp, AstNode* consumerp) {
|
||
if (debug()>=5) consumerp->dumpTree(cout,"\telimUsePre: ");
|
||
GateElimVisitor elimVisitor (consumerp, varscp, substp);
|
||
if (elimVisitor.didReplace()) {
|
||
if (debug()>=9) consumerp->dumpTree(cout,"\telimUseCns: ");
|
||
//Caution: Can't let V3Const change our handle to consumerp, such as by
|
||
// optimizing away this assignment, etc.
|
||
consumerp = V3Const::constifyEdit(consumerp);
|
||
if (debug()>=5) consumerp->dumpTree(cout,"\telimUseDne: ");
|
||
}
|
||
}
|
||
|
||
//######################################################################
|
||
// Convert VARSCOPE(ASSIGN(default, VARREF)) to just VARSCOPE(default)
|
||
|
||
class GateDeassignVisitor : public GateBaseVisitor {
|
||
private:
|
||
// VISITORS
|
||
virtual void visit(AstVarScope* nodep, AstNUser*) {
|
||
if (AstNodeAssign* assp = nodep->valuep()->castNodeAssign()) {
|
||
UINFO(5," Removeassign "<<assp<<endl);
|
||
AstNode* valuep = assp->rhsp();
|
||
valuep->unlinkFrBack();
|
||
assp->replaceWith(valuep);
|
||
assp->deleteTree(); assp=NULL;
|
||
}
|
||
}
|
||
// Speedups
|
||
virtual void visit(AstVar* nodep, AstNUser*) {}
|
||
virtual void visit(AstActive* nodep, AstNUser*) {}
|
||
virtual void visit(AstNode* nodep, AstNUser*) {
|
||
nodep->iterateChildren(*this);
|
||
}
|
||
|
||
public:
|
||
// CONSTUCTORS
|
||
GateDeassignVisitor(AstNode* nodep) {
|
||
nodep->accept(*this);
|
||
}
|
||
virtual ~GateDeassignVisitor() {}
|
||
};
|
||
|
||
//######################################################################
|
||
// Gate class functions
|
||
|
||
void V3Gate::gateAll(AstNetlist* nodep) {
|
||
UINFO(2,__FUNCTION__<<": "<<endl);
|
||
GateVisitor visitor (nodep);
|
||
GateDeassignVisitor deassign (nodep);
|
||
}
|