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46 lines
1.5 KiB
Verilog
46 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"};
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initial begin
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$display("%s", SVEC[3'd1]);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
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"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"};
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function string regx (logic [5-1:0] r, bit abi=1'b0);
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regx = abi ? REGX[r] : $sformatf("x%0d", r);
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endfunction: regx
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function string dis32 (logic [32-1:0] op);
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casez (op)
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32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop");
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32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-");
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32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)",
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regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0]));
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default: dis32 = "illegal";
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endcase
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endfunction: dis32
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always @(posedge clk) begin
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for (int unsigned i=0; i<32; i++)
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$display("REGX: %s", regx(i[4:0]));
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$display("OP: %s", dis32(32'h00000000));
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$finish();
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end
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endmodule
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