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13 lines
292 B
Verilog
13 lines
292 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t;
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integer i;
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generate
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for (i=0; i<3; i=i+1) begin // Bad: i is not a genvar
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end
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endgenerate
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endmodule
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