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27 lines
542 B
Systemverilog
27 lines
542 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#221
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Julien Margetts (Originally provided by Adrien Le Masle)
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// SPDX-License-Identifier: Unlicense
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module verilator_latch
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(
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input logic state,
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output logic [31:0] b
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);
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function logic [31:0 ] toto ();
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logic [31:0] res;
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res = 10;
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return res;
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endfunction
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always_comb
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begin
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b = 0;
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if (state)
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b = toto();
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end
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endmodule;
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