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71 lines
1.5 KiB
Systemverilog
71 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int f;
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function new(int x);
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f = x;
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endfunction
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endclass
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class ExtendCls extends Cls;
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function new(int x);
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super.new(x);
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endfunction
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endclass
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class AnotherExtendCls extends Cls;
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function new(int x);
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super.new(x);
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endfunction
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endclass
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class ExtendExtendCls extends ExtendCls;
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function new(int x);
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super.new(x);
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls cls1 = null, cls2 = null;
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ExtendCls ext_cls = null;
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AnotherExtendCls an_ext_cls = null;
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ExtendExtendCls ext_ext_cls = null;
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cls1 = (cls1 == null) ? cls2 : cls1;
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if (cls1 != null) $stop;
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cls1 = new(1);
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cls1 = (cls1 == null) ? cls2 : cls1;
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if (cls1.f != 1) $stop;
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cls1 = (cls1 != null) ? cls2 : cls1;
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if (cls1 != null) $stop;
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cls1 = new(1);
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cls2 = new(2);
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cls1 = (cls1 != null) ? cls2 : cls1;
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if (cls1.f != 2) $stop;
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cls1 = null;
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cls1 = (ext_cls != null) ? ext_cls : cls2;
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if (cls1.f != 2) $stop;
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ext_cls = new(3);
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cls1 = (ext_cls != null) ? ext_cls : cls2;
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if (cls1.f != 3) $stop;
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ext_ext_cls = new(4);
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an_ext_cls = new(5);
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cls1 = (ext_ext_cls.f != 4) ? ext_ext_cls : an_ext_cls;
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if (cls1.f != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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