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79 lines
1.4 KiB
Systemverilog
79 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Driss Hafdi.
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// SPDX-License-Identifier: CC0-1.0
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`begin_keywords "VAMS-2.3"
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module t (/*AUTOARG*/);
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// Just get errors on bad keywords (for code coverage)
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int above;
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int abs;
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int absdelay;
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int abstol;
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int ac_stim;
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int access;
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int acos;
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int acosh;
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int aliasparam;
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int analog;
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int analysis;
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int assert;
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int branch;
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int connect;
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int connectmodule;
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int connectrules;
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int continuous;
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int cross;
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int ddt;
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int ddt_nature;
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int ddx;
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int discipline;
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int discrete;
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int domain;
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int driver_update;
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int endconnectrules;
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int enddiscipline;
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int endnature;
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int endparamset;
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int exclude;
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int final_step;
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int flicker_noise;
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int flow;
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int from;
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int ground;
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int idt;
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int idt_nature;
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int idtmod;
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int inf;
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int initial_step;
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int laplace_nd;
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int laplace_np;
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int laplace_zd;
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int laplace_zp;
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int last_crossing;
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int limexp;
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int max;
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int merged;
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int min;
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int nature;
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int net_resolution;
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int noise_table;
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int paramset;
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int potential;
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int resolveto;
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int slew;
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int split;
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int timer;
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int transition;
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int units;
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int white_noise;
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int zi_nd;
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int zi_np;
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int zi_zd;
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int zi_zp;
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endmodule
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