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15 lines
349 B
Systemverilog
15 lines
349 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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reg [72:1] in;
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initial begin
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if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop;
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end
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endmodule
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