mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 00:27:35 +00:00
22 lines
375 B
Systemverilog
22 lines
375 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2014 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
`define CHECK text \
|
|
multiline
|
|
|
|
Hello in t_preproc_psl.v
|
|
|
|
`ifdef NEVER
|
|
not
|
|
`else
|
|
yes
|
|
`endif
|
|
|
|
Multi `CHECK line
|
|
|
|
// Did we end up right?
|
|
Line: `__LINE__
|