mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 00:27:35 +00:00
12 lines
286 B
Systemverilog
12 lines
286 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2019 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
`resetall // Ok
|
|
module t;
|
|
`resetall // Bad
|
|
endmodule
|
|
`resetall // Ok
|