verilator/ex_DIDNOTCONVERGE_nodbg_msg.rst at 94fd17e4f73ab3f34308b58ebbb98f04617fc506 - verilator - Gitea: Git with a cup of tea

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Geza Lore 599d23697d

IEEE compliant scheduler (#3384 )

This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278

2022-05-15 16:03:32 +01:00

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 .. comment: generated by t_lint_didnotconverge_nodbg_bad
 .. code-block::
    %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.