verilator/test_regress/t/t_trace_complex_structs.out
2014-03-14 20:36:47 -04:00

289 lines
3.3 KiB
Plaintext

$version Generated by VerilatedVcd $end
$date Fri Mar 14 20:32:11 2014
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 B clk $end
$scope module $unit $end
$var wire 1 # global_bit $end
$upscope $end
$scope module v $end
$var wire 1 B clk $end
$var wire 32 $ cyc [31:0] $end
$var real 64 < v_arr_real(0) $end
$var real 64 > v_arr_real(1) $end
$var wire 2 - v_arrp [2:1] $end
$var wire 2 . v_arrp_arrp(3) [1:0] $end
$var wire 2 / v_arrp_arrp(4) [1:0] $end
$var wire 1 C v_arru(1) $end
$var wire 1 D v_arru(2) $end
$var wire 2 4 v_arru_arrp(3) [2:1] $end
$var wire 2 5 v_arru_arrp(4) [2:1] $end
$var wire 1 E v_arru_arru(3)(1) $end
$var wire 1 F v_arru_arru(3)(2) $end
$var wire 1 G v_arru_arru(4)(1) $end
$var wire 1 H v_arru_arru(4)(2) $end
$var real 64 : v_real $end
$scope module unnamedblk1 $end
$var wire 32 @ b [31:0] $end
$scope module unnamedblk2 $end
$var wire 32 A a [31:0] $end
$upscope $end
$upscope $end
$scope module v_arrp_strp(3) $end
$var wire 1 1 b0 $end
$var wire 1 0 b1 $end
$upscope $end
$scope module v_arrp_strp(4) $end
$var wire 1 3 b0 $end
$var wire 1 2 b1 $end
$upscope $end
$scope module v_arru_strp(3) $end
$var wire 1 7 b0 $end
$var wire 1 6 b1 $end
$upscope $end
$scope module v_arru_strp(4) $end
$var wire 1 9 b0 $end
$var wire 1 8 b1 $end
$upscope $end
$scope module v_strp $end
$var wire 1 & b0 $end
$var wire 1 % b1 $end
$upscope $end
$scope module v_strp_strp $end
$scope module x0 $end
$var wire 1 * b0 $end
$var wire 1 ) b1 $end
$upscope $end
$scope module x1 $end
$var wire 1 ( b0 $end
$var wire 1 ' b1 $end
$upscope $end
$upscope $end
$scope module v_unip_strp $end
$scope module x0 $end
$var wire 1 , b0 $end
$var wire 1 + b1 $end
$upscope $end
$scope module x1 $end
$var wire 1 , b0 $end
$var wire 1 + b1 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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