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60 lines
1.8 KiB
Systemverilog
60 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// This checks IEEE ports work correctly, we use XML output to make it easy to
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// see all attributes are propagated
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// verilator lint_off MULTITOP
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`ifndef VERILATOR
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module mh0 (wire x_inout_wire_logic);
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endmodule
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module mh1 (integer x_inout_wire_integer);
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endmodule
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`endif
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module mh2 (inout integer x_inout_wire_integer);
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endmodule
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`ifndef VERILATOR
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module mh3 ([5:0] x_inout_wire_logic_p6);
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endmodule
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`endif
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module mh5 (input x_input_wire_logic);
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endmodule
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module mh6 (input var x_input_var_logic);
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endmodule
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module mh7 (input var integer x_input_var_integer);
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endmodule
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module mh8 (output x_output_wire_logic);
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endmodule
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module mh9 (output var x_output_var_logic);
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endmodule
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module mh10(output signed [5:0] x_output_wire_logic_signed_p6);
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endmodule
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module mh11(output integer x_output_var_integer);
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endmodule
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module mh12(ref [5:0] x_ref_logic_p6);
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endmodule
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module mh13(ref x_ref_var_logic_u6 [5:0]);
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endmodule
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`ifndef VERILATOR
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module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]);
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endmodule
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module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6);
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endmodule
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module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic);
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endmodule
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`endif
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module mh17(input var integer x_input_var_integer, wire y_input_wire_logic);
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endmodule
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module mh18(output var x_output_var_logic, input y_input_wire_logic);
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endmodule
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module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer);
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endmodule
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module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6);
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endmodule
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module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic);
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endmodule
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