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32 lines
619 B
Systemverilog
32 lines
619 B
Systemverilog
// DESCRIPTION::Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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int unsigned id = 0;
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function int unsigned func();
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int unsigned local_id;
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local_id = id + 1;
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id = local_id;
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return local_id;
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endfunction : func
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endpackage
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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import pkg::*;
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int unsigned func_id = func();
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always @ (posedge clk) begin
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$display(id);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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