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https://github.com/verilator/verilator.git
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95c4ade718
This patch adds some abstract enums to pass to the trace decl* APIs, so
the VCD/FST specific code can be kept in verilated_{vcd,fst}_*.cc, and
removed from V3Emit*. It also reworks the generation of the trace init
functions (those that call 'decl*' for the signals) such that the scope
hierarchy is traversed precisely once during initialization, which
simplifies the FST writer. This later change also has the side effect of
fixing tracing of nested interfaces when traced via an interface
reference - see the change in the expected t_interface_ref_trace - which
previously were missed.
289 lines
4.8 KiB
Plaintext
289 lines
4.8 KiB
Plaintext
$date
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Tue Oct 24 11:09:24 2023
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$end
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$version
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fstWriter
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$scope module $unit $end
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$var bit 1 ! global_bit $end
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$upscope $end
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$scope module t $end
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$var wire 1 " clk $end
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$var integer 32 # cyc [31:0] $end
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$var bit 2 $ v_strp [1:0] $end
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$var bit 4 % v_strp_strp [3:0] $end
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$var bit 2 & v_unip_strp [1:0] $end
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$var bit 2 ' v_arrp [2:1] $end
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$var bit 4 ( v_arrp_arrp [3:0] $end
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$var bit 4 ) v_arrp_strp [3:0] $end
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$var bit 1 * v_arru[1] $end
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$var bit 1 + v_arru[2] $end
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$var bit 1 , v_arru_arru[3][1] $end
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$var bit 1 - v_arru_arru[3][2] $end
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$var bit 1 . v_arru_arru[4][1] $end
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$var bit 1 / v_arru_arru[4][2] $end
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$var bit 2 0 v_arru_arrp[3] [2:1] $end
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$var bit 2 1 v_arru_arrp[4] [2:1] $end
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$var bit 2 2 v_arru_strp[3] [1:0] $end
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$var bit 2 3 v_arru_strp[4] [1:0] $end
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$var real 64 4 v_real $end
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$var real 64 5 v_arr_real[0] $end
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$var real 64 6 v_arr_real[1] $end
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$var logic 64 7 v_str32x2 [63:0] $end
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$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
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$attrbegin misc 07 "" 1 $end
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$var int 32 8 v_enumed [31:0] $end
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$attrbegin misc 07 "" 1 $end
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$var int 32 9 v_enumed2 [31:0] $end
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$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
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$attrbegin misc 07 "" 2 $end
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$var logic 3 : v_enumb [2:0] $end
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$var logic 6 ; v_enumb2_str [5:0] $end
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$var logic 8 < unpacked_array[-2] [7:0] $end
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$var logic 8 = unpacked_array[-1] [7:0] $end
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$var logic 8 > unpacked_array[0] [7:0] $end
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$var bit 1 ? LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
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$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
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$var parameter 32 @ PARAM [31:0] $end
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$upscope $end
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$scope module p2 $end
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$var parameter 32 A PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var parameter 32 B PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var integer 32 C b [31:0] $end
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$scope module unnamedblk2 $end
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$var integer 32 D a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b00000000000000000000000000000000 D
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b00000000000000000000000000000000 C
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b00000000000000000000000000000011 B
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b00000000000000000000000000000010 A
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b00000000000000000000000000000100 @
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0?
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b00000000 >
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b00000000 =
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b00000000 <
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b000000 ;
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b000 :
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b00000000000000000000000000000000 9
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b00000000000000000000000000000000 8
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b0000000000000000000000000000000000000000000000000000000011111111 7
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r0 6
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r0 5
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r0 4
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b00 3
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b00 2
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b00 0
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b00000000000000000000000000000000 #
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1!
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$end
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#10
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1"
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b00000000000000000000000000000001 #
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b11 $
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b1111 %
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b11 2
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b11 3
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r0.1 4
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r0.2 5
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r0.3 6
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b0000000000000000000000000000000100000000000000000000000011111110 7
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b00000000000000000000000000000001 8
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b00000000000000000000000000000010 9
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b111 :
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b00000000000000000000000000000101 C
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b00000000000000000000000000000101 D
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#11
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#12
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#14
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0"
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#20
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1"
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b110 :
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b00000000000000000000000000000100 9
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b00000000000000000000000000000010 8
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b0000000000000000000000000000001000000000000000000000000011111101 7
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r0.6 6
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r0.4 5
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r0.2 4
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b00 3
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b00 2
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b00 1
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b00 0
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b0000 )
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b0000 (
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b00000000000000000000000000000010 #
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b111111 ;
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#21
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#22
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#23
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#24
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#25
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0"
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#26
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#27
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#28
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#29
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#30
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1"
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b110110 ;
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b00000000000000000000000000000011 #
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b11 $
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b1111 %
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b11 &
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b11 '
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b1111 (
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b1111 )
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b11 0
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b11 1
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b11 2
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b11 3
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r0.3 4
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r0.6000000000000001 5
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r0.8999999999999999 6
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b0000000000000000000000000000001100000000000000000000000011111100 7
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b00000000000000000000000000000011 8
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b00000000000000000000000000000110 9
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b101 :
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#31
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#32
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#34
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#35
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0"
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#38
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#39
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1"
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b100 :
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b00000000000000000000000000001000 9
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b00000000000000000000000000000100 8
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b0000000000000000000000000000010000000000000000000000000011111011 7
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r1.2 6
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r0.8 5
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r0.4 4
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b00 3
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b00 2
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b00 1
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b00 0
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b0000 )
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b0000 (
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b00 '
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b00 &
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b0000 %
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b00000000000000000000000000000100 #
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b101101 ;
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0"
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#50
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1"
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b100100 ;
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b00000000000000000000000000000101 #
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b11 $
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b1111 %
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b11 &
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b11 '
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b1111 )
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b11 0
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b11 1
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b11 2
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b11 3
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r0.5 4
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r1 5
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r1.5 6
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b0000000000000000000000000000010100000000000000000000000011111010 7
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b00000000000000000000000000000101 8
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b00000000000000000000000000001010 9
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b011 :
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0"
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#59
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#60
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1"
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b010 :
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b00000000000000000000000000001100 9
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b00000000000000000000000000000110 8
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b0000000000000000000000000000011000000000000000000000000011111001 7
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r1.8 6
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r1.2 5
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r0.6 4
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b00 3
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b00 2
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b00 1
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b0000 )
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b0000 (
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b00000000000000000000000000000110 #
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b011011 ;
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#61
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#63
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#64
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