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104 lines
2.4 KiB
Verilog
104 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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bit global_bit;
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module t (clk);
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input clk;
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integer cyc=0;
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typedef struct packed {
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bit b1;
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bit b0;
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} strp_t;
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typedef struct packed {
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strp_t x1;
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strp_t x0;
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} strp_strp_t;
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typedef union packed {
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strp_t x1;
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strp_t x0;
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} unip_strp_t;
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typedef bit [2:1] arrp_t;
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typedef arrp_t [4:3] arrp_arrp_t;
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typedef strp_t [4:3] arrp_strp_t;
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typedef bit arru_t [2:1];
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typedef arru_t arru_arru_t [4:3];
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typedef arrp_t arru_arrp_t [4:3];
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typedef strp_t arru_strp_t [4:3];
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strp_t v_strp;
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strp_strp_t v_strp_strp;
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unip_strp_t v_unip_strp;
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arrp_t v_arrp;
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arrp_arrp_t v_arrp_arrp;
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arrp_strp_t v_arrp_strp;
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arru_t v_arru;
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arru_arru_t v_arru_arru;
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arru_arrp_t v_arru_arrp;
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arru_strp_t v_arru_strp;
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real v_real;
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real v_arr_real [2];
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string v_string;
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typedef struct packed {
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logic [31:0] data;
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} str32_t;
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str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0
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initial v_str32x2[0] = 32'hff;
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initial v_str32x2[1] = 0;
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typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t;
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enumed_t v_enumed;
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enumed_t v_enumed2;
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typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t;
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enumb_t v_enumb;
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p #(.PARAM(2)) p2 ();
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p #(.PARAM(3)) p3 ();
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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v_strp <= ~v_strp;
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v_strp_strp <= ~v_strp_strp;
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v_unip_strp <= ~v_unip_strp;
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v_arrp_strp <= ~v_arrp_strp;
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v_arrp <= ~v_arrp;
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v_arrp_arrp <= ~v_arrp_arrp;
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v_real <= v_real + 0.1;
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v_string <= cyc[0] ? "foo" : "bar";
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v_arr_real[0] <= v_arr_real[0] + 0.2;
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v_arr_real[1] <= v_arr_real[1] + 0.3;
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v_enumed <= v_enumed + 1;
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v_enumed2 <= v_enumed2 + 2;
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v_enumb <= v_enumb - 1;
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for (integer b=3; b<=4; b++) begin
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v_arru[b] <= ~v_arru[b];
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v_arru_strp[b] <= ~v_arru_strp[b];
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v_arru_arrp[b] <= ~v_arru_arrp[b];
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for (integer a=3; a<=4; a++) begin
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v_arru_arru[a][b] = ~v_arru_arru[a][b];
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end
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end
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v_str32x2[0] <= v_str32x2[0] - 1;
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v_str32x2[1] <= v_str32x2[1] + 1;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module p;
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parameter PARAM = 1;
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initial global_bit = 1;
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endmodule
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