mirror of
https://github.com/verilator/verilator.git
synced 2025-01-07 15:17:36 +00:00
29 lines
446 B
Verilog
29 lines
446 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2017 by Wilson Snyder.
|
|
|
|
interface dummy_if ();
|
|
logic sig_udrv;
|
|
logic sig_uusd;
|
|
endinterface: dummy_if
|
|
|
|
module sub
|
|
(
|
|
dummy_if dummy
|
|
);
|
|
|
|
assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv;
|
|
endmodule
|
|
|
|
|
|
module t (/*AUTOARG*/);
|
|
|
|
dummy_if dummy ();
|
|
|
|
sub sub
|
|
(.dummy(dummy)
|
|
);
|
|
|
|
endmodule
|