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34 lines
694 B
Verilog
34 lines
694 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire d, en, nc, pc;
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// verilator lint_off IMPLICIT
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cmos (cm0, d, nc, pc);
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rcmos (rc0, d, nc, pc);
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nmos (nm0, d, en);
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pmos (pm0, d, en);
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rnmos (rn0, d, en);
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rpmos (rp0, d, en);
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rtran (rt0, d);
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tran (tr0, d);
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rtranif0 (r00, d, en);
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rtranif1 (r10, d, en);
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tranif0 (t00, d, en);
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tranif1 (t10, d, en);
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// verilator lint_on IMPLICIT
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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