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82 lines
1.7 KiB
Verilog
82 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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typedef enum logic [4:0]
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{
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BIT0 = 5'd0,
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BIT1 = 5'd1,
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BIT2 = 5'd2
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} three_t;
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module t (/*AUTOARG*/);
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localparam FIVE = 5;
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enum { e0,
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e1,
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e3=3,
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e5=FIVE,
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e10_[2] = 10,
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e12,
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e20_[5:7] = 25,
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e20_z,
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e30_[7:5] = 30,
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e30_z
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} EN;
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enum {
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z5 = e5
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} ZN;
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typedef enum [2:0] { ONES=~0 } three_t;
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three_t three = ONES;
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var logic [ONES:0] sized_based_on_enum;
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var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2},
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QPR={2'b0,2'h3 }, QACK, QRSP } inv;
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initial begin
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if (e0 !== 0) $stop;
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if (e1 !== 1) $stop;
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if (e3 !== 3) $stop;
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if (e5 !== 5) $stop;
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if (e10_0 !== 10) $stop;
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if (e10_1 !== 11) $stop;
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if (e12 !== 12) $stop;
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if (e20_5 !== 25) $stop;
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if (e20_6 !== 26) $stop;
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if (e20_7 !== 27) $stop;
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if (e20_z !== 28) $stop;
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if (e30_7 !== 30) $stop;
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if (e30_6 !== 31) $stop;
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if (e30_5 !== 32) $stop;
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if (e30_z !== 33) $stop;
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if (z5 !== 5) $stop;
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if (three != 3'b111) $stop;
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if ($bits(sized_based_on_enum) != 8) $stop;
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if ($bits(three_t) != 3) $stop;
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if (FIVE[BIT0] != 1'b1) $stop;
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if (FIVE[BIT1] != 1'b0) $stop;
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if (FIVE[BIT2] != 1'b1) $stop;
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if (QINVALID != 15) $stop;
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if (QSEND != 0) $stop;
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if (QOP != 1) $stop;
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if (QCL != 2) $stop;
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if (QPR != 3) $stop;
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if (QACK != 4) $stop;
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if (QRSP != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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