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16 lines
357 B
Verilog
16 lines
357 B
Verilog
// DESCRIPTION: Verilator: $display() test for %l
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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module t (/*AUTOARG*/);
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initial begin
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assert (0 == 0) else $fatal(2, "%l %m : %d", 0);
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$display("%l %m");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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