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40 lines
1.3 KiB
Python
Executable File
40 lines
1.3 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all')
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test.pli_filename = "t/t_trace_public_sig.cpp"
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test.top_filename = "t/t_trace_public.v"
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test.golden_filename = "t/t_trace_public.out"
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out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
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test.compile(make_top_shell=False,
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make_main=False,
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v_flags2=[
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"--trace --exe", test.pli_filename,
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test.t_dir + "/t_trace_public_sig.vlt --no-json-edit-nums"
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])
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if test.vlt_all:
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"GSR",.*"loc":"\w,47:[^"]*",.*"origName":"GSR",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true'
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)
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test.execute()
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test.vcd_identical(test.trace_filename, test.golden_filename)
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# vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;"
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test.file_grep(test.trace_filename, r'module glbl')
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test.passes()
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