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40 lines
950 B
Systemverilog
40 lines
950 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class Foo;
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task sleep;
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event e;
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fork
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@e;
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#1 ->e;
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join
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endtask
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task trigger_later1(event e);
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fork #2 ->e; join_none
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endtask
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task trigger_later2(ref event e);
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fork #3 ->e; join_none
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endtask
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task test;
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for (int i = 0; i < 10; i++) begin
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event e1, e2;
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trigger_later1(e1);
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trigger_later2(e2);
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sleep;
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@e1; @e2;
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end
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endtask
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endclass
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initial begin
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Foo foo = new;
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foo.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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