mirror of
https://github.com/verilator/verilator.git
synced 2025-02-08 06:32:24 +00:00
14 lines
346 B
Systemverilog
14 lines
346 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2024 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
function void imp_func_conflict();
|
|
endfunction
|
|
|
|
`default_nettype wire
|
|
assign imp_func_conflict = 1'b1;
|
|
endmodule
|