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47 lines
1.3 KiB
Python
Executable File
47 lines
1.3 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.top_filename = os.path.join(test.obj_dir, "t_inst_long.v")
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length = 200
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longname = "long_" * int((length + 4) / 5)
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def gen_top(filename):
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with open(filename, 'w', encoding="utf8") as fh:
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fh.write("// Generated by t_inst_long.py\n")
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fh.write("module t;\n")
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fh.write("\n")
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fh.write(" " + longname + " inst ();\n")
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fh.write("\n")
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fh.write("endmodule\n")
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def gen_sub(filename):
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with open(filename, 'w', encoding="utf8") as fh:
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fh.write("// Generated by t_inst_long.py\n")
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fh.write("module " + longname + ";\n")
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fh.write("\n")
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fh.write(" initial begin\n")
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fh.write(" $write(\"*-* All Finished *-*\\n\");\n")
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fh.write(" $finish;\n")
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fh.write(" end\n")
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fh.write("endmodule\n")
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gen_top(test.top_filename)
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gen_sub(os.path.join(test.obj_dir, longname + ".v"))
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test.compile()
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test.passes()
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