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22 lines
474 B
Systemverilog
22 lines
474 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum bit [4:0] {V0 = 1} my_enum;
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class Cls;
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my_enum sp = V0;
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c = new;
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int i = 0;
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if (i inside {c.sp}) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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