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20 lines
432 B
Systemverilog
20 lines
432 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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function logic get_x_or_0(logic get_x);
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return get_x ? 1'bx : 1'b0;
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endfunction
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module t;
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initial begin
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if (1 ==? get_x_or_0(0)) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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