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31 lines
1.2 KiB
Python
Executable File
31 lines
1.2 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vltmt')
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# Use a top file which we are sure to be parallelizable
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test.top_filename = "t/t_gen_alw.v"
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test.compile(v_flags2=["--dumpi-graph 6"], threads=2)
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for dotname in [
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"linkcells", "task_call", "gate_graph", "gate_final", "acyc_simp", "orderg_pre",
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"orderg_acyc", "orderg_order", "orderg_domain", "ordermv_initial", "ordermv_hazards",
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"ordermv_contraction", "ordermv_transitive1", "orderg_done", "schedule"
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]:
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# Some files with identical prefix are generated multiple times during
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# Verilation. Ensure that at least one of each dotname-prefixed file is generated.
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dotFiles = test.glob_some(test.obj_dir + "/*" + dotname + ".dot")
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for dotFilename in dotFiles:
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test.file_grep(dotFilename, r'digraph v3graph')
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test.passes()
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