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66 lines
1.4 KiB
Systemverilog
66 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, cond) \
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begin \
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longint prev_result; \
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int ok = 0; \
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if (!bit'(cl.randomize())) $stop; \
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prev_result = longint'(field); \
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if (!(cond)) $stop; \
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repeat(9) begin \
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longint result; \
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if (!bit'(cl.randomize())) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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typedef class C;
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class D extends C;
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constraint x_lt_y { x < y; }
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endclass
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class A;
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endclass
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class B extends A;
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rand int x;
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constraint x_gt_0 { x > 0; }
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endclass
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class C extends B;
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rand int y;
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endclass
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class E extends C;
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constraint x_lt_20 { x < 20; }
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constraint x_gt_y { x > y; }
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endclass
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module t;
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initial begin
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B b = new;
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C c = new;
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D d = new;
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E e = new;
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A a = b;
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`check_rand(a, b.x, b.x > 0);
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`check_rand(c, c.x, c.x > 0);
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`check_rand(c, c.y, c.x > 0);
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`check_rand(d, d.x, d.x > 0 && d.x < d.y);
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`check_rand(d, d.y, d.x > 0 && d.x < d.y);
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`check_rand(e, e.x, e.x > 0 && e.x < 20 && e.x > e.y);
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`check_rand(e, e.y, e.x > 0 && e.x < 20 && e.x > e.y);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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