mirror of
https://github.com/verilator/verilator.git
synced 2025-02-08 06:32:24 +00:00
15 lines
345 B
Systemverilog
15 lines
345 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2024 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
class Packet;
|
|
extern constraint missing_bad;
|
|
endclass
|
|
|
|
constraint Packet::missing_extern { }
|
|
|
|
module t (/*AUTOARG*/);
|
|
endmodule
|