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40 lines
1.6 KiB
Python
Executable File
40 lines
1.6 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_clk_concat.v"
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out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
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test.compile(verilator_flags2=["--no-json-edit-nums", "t/t_clk_concat.vlt"])
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if test.vlt_all:
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"clk0",.*"loc":"\w,78:[^"]*",.*"origName":"clk0",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"'
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)
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"clk1",.*"loc":"\w,79:[^"]*",.*"origName":"clk1",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"'
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)
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"clk2",.*"loc":"\w,80:[^"]*",.*"origName":"clk2",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"clker",.*"varType":"PORT",.*"dtypeName":"logic"'
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)
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"data_in",.*"loc":"\w,82:[^"]*",.*"origName":"data_in",.*"direction":"INPUT",.*"isSigPublic":true,.*"attrClocker":"non_clker",.*"varType":"PORT",.*"dtypeName":"logic"'
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)
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test.execute()
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test.passes()
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