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33 lines
642 B
Systemverilog
33 lines
642 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Pkg;
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typedef enum {
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RED=0,
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GREEN=1,
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BLUE=2
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} color_t;
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typedef struct {
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color_t pixels[32];
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} line_t;
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typedef struct {
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line_t line[32];
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} screen_t;
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endpackage
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module t;
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Pkg::screen_t screen;
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initial begin
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screen = '{ default: '0, Pkg::color_t: Pkg::RED};
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$display("%p", screen);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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