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19 lines
637 B
Plaintext
19 lines
637 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v"
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lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 18
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// Test wildcard filenames
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lint_off -rule WIDTH -file "*/t_vlt_warn.v" -lines 19-19
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// Test global disables
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lint_off -file "*/t_vlt_warn.v" -lines 20-20
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coverage_off -file "t/t_vlt_warn.v"
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// Test --flag is also accepted
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tracing_off --file "t/t_vlt_warn.v"
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