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https://github.com/verilator/verilator.git
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8e812058cb
git-svn-id: file://localhost/svn/verilator/trunk/verilator@1039 77ca24e4-aefa-0310-84f0-b9a241c72d87
457 lines
13 KiB
C++
457 lines
13 KiB
C++
// $Id$
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//*************************************************************************
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// DESCRIPTION: Verilator: Emit Verilog from tree
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//
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// Code available from: http://www.veripool.org/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2004-2008 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// General Public License or the Perl Artistic License.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include <stdio.h>
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#include <stdarg.h>
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#include <unistd.h>
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#include <math.h>
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#include <map>
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#include <vector>
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#include <algorithm>
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#include "V3Global.h"
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#include "V3EmitV.h"
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#include "V3EmitCBase.h"
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//######################################################################
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// Emit statements and math operators
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class EmitVImp : public EmitCBaseVisitor {
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private:
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bool m_suppressSemi;
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AstModule* m_modp;
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public:
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//int debug() { return 9; }
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// METHODS
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// VISITORS
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virtual void visit(AstNetlist* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstModule* nodep, AstNUser*) {
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m_modp = nodep;
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putbs("module "+modClassName(nodep)+";\n");
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nodep->iterateChildren(*this);
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puts("endmodule\n");
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}
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virtual void visit(AstNodeFTask* nodep, AstNUser*) {
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putbs(nodep->castTask() ? "task ":"function ");
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puts(nodep->name());
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puts(";\n");
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putbs("begin\n");
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nodep->stmtsp()->iterateAndNext(*this);
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puts("end\n");
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}
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virtual void visit(AstBegin* nodep, AstNUser*) {
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putbs("begin\n");
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nodep->iterateChildren(*this);
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puts("end\n");
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}
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virtual void visit(AstGenerate* nodep, AstNUser*) {
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putbs("generate\n");
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nodep->iterateChildren(*this);
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puts("end\n");
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}
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virtual void visit(AstFinal* nodep, AstNUser*) {
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putbs("final begin\n");
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nodep->iterateChildren(*this);
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puts("end\n");
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}
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virtual void visit(AstInitial* nodep, AstNUser*) {
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putbs("initial begin\n");
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nodep->iterateChildren(*this);
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puts("end\n");
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}
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virtual void visit(AstAlways* nodep, AstNUser*) {
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putbs("always ");
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nodep->sensesp()->iterateAndNext(*this);
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putbs("begin\n");
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nodep->bodysp()->iterateAndNext(*this);
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puts("end\n");
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}
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virtual void visit(AstNodeAssign* nodep, AstNUser*) {
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nodep->lhsp()->iterateAndNext(*this);
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putbs(" "+nodep->verilogKwd()+" ");
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nodep->rhsp()->iterateAndNext(*this);
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if (!m_suppressSemi) puts(";\n");
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}
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virtual void visit(AstAssignDly* nodep, AstNUser*) {
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nodep->lhsp()->iterateAndNext(*this);
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putbs(" <= ");
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nodep->rhsp()->iterateAndNext(*this);
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puts(";\n");
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}
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virtual void visit(AstAssignAlias* nodep, AstNUser*) {
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putbs("assign ");
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nodep->lhsp()->iterateAndNext(*this);
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putbs(" = ");
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nodep->rhsp()->iterateAndNext(*this);
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if (!m_suppressSemi) puts(";\n");
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}
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virtual void visit(AstAssignW* nodep, AstNUser*) {
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putbs("assign ");
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nodep->lhsp()->iterateAndNext(*this);
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putbs(" = ");
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nodep->rhsp()->iterateAndNext(*this);
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if (!m_suppressSemi) puts(";\n");
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}
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virtual void visit(AstSenTree* nodep, AstNUser*) {
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putbs("@(");
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nodep->iterateChildren(*this);
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puts(") ");
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}
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virtual void visit(AstSenItem* nodep, AstNUser*) {
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putbs("");
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if (nodep->backp()->castSenItem()) puts(" or ");
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puts(nodep->edgeType().verilogKwd());
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puts(" ");
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nodep->iterateChildren(*this);
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puts(" ");
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}
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virtual void visit(AstNodeCase* nodep, AstNUser*) {
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putbs(nodep->verilogKwd());
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puts(" (");
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nodep->exprp()->iterateAndNext(*this);
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puts(")\n");
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if (AstCase* casep = nodep->castCase()) {
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if (casep->fullPragma() || casep->parallelPragma()) {
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puts(" // synopsys");
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if (casep->fullPragma()) puts(" full_case");
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if (casep->parallelPragma()) puts(" parallel_case");
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}
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}
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nodep->itemsp()->iterateAndNext(*this);
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putbs("endcase");
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puts("\n");
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}
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virtual void visit(AstCaseItem* nodep, AstNUser*) {
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if (nodep->condsp()) {
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nodep->condsp()->iterateAndNext(*this);
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} else putbs("default");
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putbs(": begin ");
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nodep->bodysp()->iterateAndNext(*this);
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puts("end\n");
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}
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virtual void visit(AstComment* nodep, AstNUser*) {
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puts((string)"// "+nodep->name()+"\n");
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstCoverDecl*, AstNUser*) {
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// N/A
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}
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virtual void visit(AstCoverInc*, AstNUser*) {
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// N/A
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}
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virtual void visit(AstDisplay* nodep, AstNUser*) {
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putbs(nodep->verilogKwd());
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putbs(" (");
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if (nodep->filep()) { nodep->filep()->iterateAndNext(*this); putbs(","); }
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puts("\"");
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ofp()->putsNoTracking(nodep->text());
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puts("\"");
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for (AstNode* expp=nodep->exprsp(); expp; expp = expp->nextp()) {
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puts(",");
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expp->iterateAndNext(*this);
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}
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puts(");\n");
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}
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virtual void visit(AstFOpen* nodep, AstNUser*) {
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putbs(nodep->verilogKwd());
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putbs(" (");
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if (nodep->filep()) nodep->filep()->iterateChildren(*this);
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putbs(",");
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if (nodep->filenamep()) nodep->filenamep()->iterateChildren(*this);
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putbs(",");
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if (nodep->modep()) nodep->modep()->iterateChildren(*this);
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puts(");\n");
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}
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virtual void visit(AstFClose* nodep, AstNUser*) {
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putbs(nodep->verilogKwd());
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putbs(" (");
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if (nodep->filep()) nodep->filep()->iterateChildren(*this);
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puts(");\n");
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}
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virtual void visit(AstReadMem* nodep, AstNUser*) {
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putbs(nodep->verilogKwd());
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putbs(" (");
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if (nodep->filenamep()) nodep->filenamep()->iterateChildren(*this);
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putbs(",");
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if (nodep->memp()) nodep->memp()->iterateChildren(*this);
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if (nodep->lsbp()) { putbs(","); nodep->lsbp()->iterateChildren(*this); }
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if (nodep->msbp()) { putbs(","); nodep->msbp()->iterateChildren(*this); }
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puts(");\n");
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}
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virtual void visit(AstNodeFor* nodep, AstNUser*) {
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puts("for (");
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m_suppressSemi = true;
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nodep->initsp()->iterateAndNext(*this);
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puts(";");
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nodep->condp()->iterateAndNext(*this);
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puts(";");
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nodep->incsp()->iterateAndNext(*this);
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m_suppressSemi = false;
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puts(") {\n");
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nodep->bodysp()->iterateAndNext(*this);
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puts("}\n");
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}
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virtual void visit(AstWhile* nodep, AstNUser*) {
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nodep->precondsp()->iterateAndNext(*this);
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puts("while (");
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nodep->condp()->iterateAndNext(*this);
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puts(") {\n");
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nodep->bodysp()->iterateAndNext(*this);
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nodep->precondsp()->iterateAndNext(*this); // Need to recompute before next loop
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puts("}\n");
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}
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virtual void visit(AstNodeIf* nodep, AstNUser*) {
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puts("if (");
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nodep->condp()->iterateAndNext(*this);
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puts(") begin\n");
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nodep->ifsp()->iterateAndNext(*this);
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if (nodep->elsesp()) {
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puts("end\n");
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puts("else begin\n");
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nodep->elsesp()->iterateAndNext(*this);
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}
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puts("end\n");
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}
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virtual void visit(AstStop*, AstNUser*) {
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putbs("$stop;\n");
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}
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virtual void visit(AstFinish*, AstNUser*) {
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putbs("$finish;\n");
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}
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virtual void visit(AstText* nodep, AstNUser*) {
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ofp()->putsNoTracking(nodep->text());
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}
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virtual void visit(AstScopeName* nodep, AstNUser*) {
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}
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virtual void visit(AstCStmt* nodep, AstNUser*) {
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putbs("$_CSTMT(");
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nodep->bodysp()->iterateAndNext(*this);
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puts(");\n");
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}
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virtual void visit(AstCMath* nodep, AstNUser*) {
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putbs("$_CMATH(");
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nodep->bodysp()->iterateAndNext(*this);
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puts(");\n");
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}
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virtual void visit(AstUCStmt* nodep, AstNUser*) {
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putbs("$c(");
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nodep->bodysp()->iterateAndNext(*this);
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puts(");\n");
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}
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virtual void visit(AstUCFunc* nodep, AstNUser*) {
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putbs("$c(");
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nodep->bodysp()->iterateAndNext(*this); puts(")\n");
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}
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// Operators
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virtual void emitVerilogFormat(AstNode* nodep, const string& format,
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AstNode* lhsp=NULL, AstNode* rhsp=NULL, AstNode* thsp=NULL) {
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// Look at emitVerilog() format for term/uni/dual/triops,
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// and write out appropriate text.
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// %l lhsp - if appropriate
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// %r rhsp - if appropriate
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// %t thsp - if appropriate
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// %k Potential line break
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bool inPct = false;
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putbs("");
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for (string::const_iterator pos = format.begin(); pos != format.end(); ++pos) {
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if (pos[0]=='%') {
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inPct = true;
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} else if (!inPct) { // Normal text
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string s; s+=pos[0]; puts(s);
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} else { // Format character
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inPct = false;
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switch (*pos) {
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case '%': puts("%"); break;
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case 'k': putbs(""); break;
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case 'l': {
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if (!lhsp) { nodep->v3fatalSrc("emitVerilog() references undef node"); }
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else lhsp->iterateAndNext(*this);
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break;
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}
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case 'r': {
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if (!rhsp) { nodep->v3fatalSrc("emitVerilog() references undef node"); }
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else rhsp->iterateAndNext(*this);
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break;
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}
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case 't': {
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if (!thsp) { nodep->v3fatalSrc("emitVerilog() references undef node"); }
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else thsp->iterateAndNext(*this);
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break;
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}
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default:
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nodep->v3fatalSrc("Unknown emitVerilog format code: %"<<pos[0]);
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break;
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}
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}
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}
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}
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virtual void visit(AstNodeTermop* nodep, AstNUser*) {
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emitVerilogFormat(nodep, nodep->emitVerilog());
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}
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virtual void visit(AstNodeUniop* nodep, AstNUser*) {
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emitVerilogFormat(nodep, nodep->emitVerilog(), nodep->lhsp());
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}
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virtual void visit(AstNodeBiop* nodep, AstNUser*) {
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emitVerilogFormat(nodep, nodep->emitVerilog(), nodep->lhsp(), nodep->rhsp());
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}
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virtual void visit(AstNodeTriop* nodep, AstNUser*) {
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emitVerilogFormat(nodep, nodep->emitVerilog(), nodep->lhsp(), nodep->rhsp(), nodep->thsp());
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}
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virtual void visit(AstAttrOf* nodep, AstNUser*) {
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puts("$_ATTROF(");
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nodep->fromp()->iterateAndNext(*this);
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puts(")");
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}
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virtual void visit(AstNodeCond* nodep, AstNUser*) {
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putbs("(");
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nodep->condp()->iterateAndNext(*this); putbs(" ? ");
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nodep->expr1p()->iterateAndNext(*this); putbs(" : ");
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nodep->expr2p()->iterateAndNext(*this); puts(")");
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}
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virtual void visit(AstRange* nodep, AstNUser*) {
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puts("[");
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nodep->msbp()->iterateAndNext(*this); puts(":");
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nodep->lsbp()->iterateAndNext(*this); puts("]");
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}
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virtual void visit(AstSel* nodep, AstNUser*) {
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nodep->fromp()->iterateAndNext(*this); puts("[");
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if (nodep->lsbp()->castConst()) {
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if (nodep->widthp()->isOne()) {
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nodep->lsbp()->iterateAndNext(*this);
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} else {
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puts(cvtToStr(nodep->lsbp()->castConst()->asInt()
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+nodep->widthp()->castConst()->asInt()
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-1));
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puts(":");
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nodep->lsbp()->iterateAndNext(*this);
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}
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} else {
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nodep->lsbp()->iterateAndNext(*this); puts("+:");
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nodep->widthp()->iterateAndNext(*this); puts("]");
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}
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puts("]");
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}
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virtual void visit(AstNodeFTaskRef* nodep, AstNUser*) {
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if (nodep->dotted()!="") { puts(nodep->dotted()); puts("."); }
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puts(nodep->name());
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puts("(");
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nodep->pinsp()->iterateAndNext(*this);
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puts(")");
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}
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// Terminals
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virtual void visit(AstVarRef* nodep, AstNUser*) {
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puts(nodep->hiername());
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puts(nodep->varp()->name());
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}
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virtual void visit(AstVarXRef* nodep, AstNUser*) {
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puts(nodep->dotted());
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puts(".");
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puts(nodep->varp()->name());
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}
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virtual void visit(AstConst* nodep, AstNUser*) {
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puts(nodep->num().ascii(true,true));
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}
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// Just iterate
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virtual void visit(AstTopScope* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstScope* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstVar* nodep, AstNUser*) {
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puts(nodep->verilogKwd());
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puts(" ");
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if (nodep->isSigned()) puts("signed ");
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if (nodep->rangep()) {
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puts("["+cvtToStr(nodep->msb())
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+":"+cvtToStr(nodep->lsb())
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+"] ");
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}
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puts(nodep->name());
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for (AstRange* arrayp=nodep->arraysp(); arrayp; arrayp = arrayp->nextp()->castRange()) {
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puts(" ["+cvtToStr(arrayp->msbConst())
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+":"+cvtToStr(arrayp->lsbConst())
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+"]");
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}
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puts(";\n");
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}
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virtual void visit(AstNodeText*, AstNUser*) {}
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virtual void visit(AstTraceDecl*, AstNUser*) {}
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virtual void visit(AstTraceInc*, AstNUser*) {}
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// NOPs
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virtual void visit(AstPragma*, AstNUser*) {}
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virtual void visit(AstCell*, AstNUser*) {} // Handled outside the Visit class
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// Default
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virtual void visit(AstNode* nodep, AstNUser*) {
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puts((string)"\n???? // "+nodep->typeName()+"\n");
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nodep->iterateChildren(*this);
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nodep->v3fatalSrc("Unknown node type reached emitter: "<<nodep->typeName());
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}
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public:
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EmitVImp() {
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m_suppressSemi = false;
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m_modp = NULL;
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}
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void main(AstNode* nodep, V3OutCFile* ofp);
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virtual ~EmitVImp() {}
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};
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//######################################################################
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void EmitVImp::main(AstNode* modp, V3OutCFile* ofp) {
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// Output a module, or overall netlist
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m_ofp = ofp;
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modp->accept(*this);
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}
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//######################################################################
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// EmitV class functions
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void V3EmitV::emitv() {
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UINFO(2,__FUNCTION__<<": "<<endl);
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if (1) {
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// All-in-one file
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V3OutVFile of (v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__Vout.v");
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of.putsHeader();
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EmitVImp imp;
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imp.main(v3Global.rootp(), &of);
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} else {
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// Process each module in turn
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for (AstModule* modp = v3Global.rootp()->modulesp(); modp; modp=modp->nextp()->castModule()) {
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EmitVImp imp;
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V3OutVFile of (v3Global.opt.makeDir()+"/"+imp.modClassName(modp)+"__Vout.v");
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of.putsHeader();
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imp.main(modp, &of);
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}
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}
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}
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