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72 lines
2.2 KiB
Systemverilog
Executable File
72 lines
2.2 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(
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clk
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/*AUTOARG*/);
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input clk;
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wor [3:0] ptrior1;
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trior [3:0] ptrior2;
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wand [3:0] ptriand1;
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triand [3:0] ptriand2;
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wire [3:0] z1;
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wire [3:0] z2;
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wire [3:0] tri_z1;
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wire [3:0] tri_z2;
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logic [3:0] x;
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logic [3:0] y;
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logic [3:0] tri_x;
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logic [3:0] tri_y;
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logic [3:0] tri_x_dat;
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logic [3:0] tri_y_dat;
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logic [3:0] tri_x_en;
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logic [3:0] tri_y_en;
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assign ptrior1 = x & y;
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assign ptrior1 = x + y;
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assign ptrior2 = tri_x & tri_y;
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assign ptrior2 = tri_x + tri_y;
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assign ptriand1 = x & y;
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assign ptriand1 = x + y;
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assign ptriand2 = tri_x & tri_y;
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assign ptriand2 = tri_x + tri_y;
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assign z1 = (x & y) | (x + y);
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assign z2 = (x & y) & (x + y);
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assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y);
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assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y);
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integer cyc = 0;
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integer xz_index = 0;
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integer xz_num = 0;
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integer i;
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assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz;
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assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz;
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assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz;
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assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz;
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assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz;
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assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz;
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assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz;
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assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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x = {$random}[3:0];
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y = {$random}[3:0];
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tri_x_dat = {$random}[3:0];
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tri_y_dat = {$random}[3:0];
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tri_x_en = {$random}[3:0];
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tri_y_en = {$random}[3:0];
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`checkb(ptrior1, z1);
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`checkb(ptrior2, tri_z1);
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`checkb(ptriand1, z2);
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`checkb(ptriand2, tri_z2);
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if (cyc == 20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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