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54 lines
1.6 KiB
Python
Executable File
54 lines
1.6 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = test.obj_dir + "/t_gate_chained.v"
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def gen(filename):
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with open(filename, 'w', encoding="utf8") as fh:
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fh.write("// Generated by t_gate_chained.py\n")
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fh.write("module t (clk,i,sel,o);\n")
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fh.write(" input clk;\n")
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fh.write(" input [63:0] i;\n")
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fh.write(" input [15:0] sel;\n")
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fh.write(" output [63:0] o;\n")
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fh.write("\n")
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prev = "i"
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n = 9000
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for i in range(1, n):
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fh.write(
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(" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : " + prev + ";\n") % (i, i))
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prev = "ass%04x" % i
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fh.write("\n")
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fh.write(" wire [63:0] o = " + prev + ";\n")
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fh.write("\n")
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fh.write(" always @ (posedge clk) begin\n")
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fh.write(' $write("*-* All Finished *-*\\n");' + "\n")
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fh.write(' $finish;' + "\n")
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fh.write(" end\n")
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fh.write("endmodule\n")
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gen(test.top_filename)
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test.compile(
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verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS -fno-dfg"])
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test.execute()
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# Must be <<9000 above to prove this worked
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test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8575)
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test.passes()
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