verilator/test_regress/t/t_constraint_nosolver_bad.out
2024-09-04 20:10:05 -04:00

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Process::open: execvp(someimaginarysolver): No such file or directory
%Warning: Subprocess command `someimaginarysolver' failed: exit status 127
%Warning: Unable to communicate with SAT solver, please check its installation or specify a different one in VERILATOR_SOLVER environment variable.
... Tried: $ someimaginarysolver
%Error: t/t_constraint.v:23: Verilog $stop
Aborting...