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49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class uvm_reg;
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function int get_1;
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return 1;
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endfunction
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function bit get_true;
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return 1;
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endfunction
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function string get_string;
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if (get_1() == 1) begin
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return get_true() ? "user backdoor" : "DPI backdoor";
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end else begin
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return "";
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end
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endfunction
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endclass
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class T;
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function automatic string return_str(input string a_string);
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return a_string;
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endfunction
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static function automatic string static_return_str(input string a_string);
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return a_string;
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endfunction
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endclass
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initial begin
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T t_c = new;
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uvm_reg u_r = new;
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if (u_r.get_string() != "user backdoor") $stop;
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if (t_c.return_str("A") != "A") $stop;
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if (t_c.static_return_str("B") != "B") $stop;
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if (T::static_return_str("C") != "C") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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