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24 lines
582 B
Systemverilog
24 lines
582 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Ethan Sifferman.
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// SPDX-License-Identifier: CC0-1.0
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module DECLFILENAME;
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logic UNUSEDSIGNAL;
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logic [0:1] ASCRANGE_UNDRIVEN;
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always_comb begin
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case (ASCRANGE_UNDRIVEN)
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2'b0x: UNUSEDSIGNAL = 1;
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endcase
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end
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`ifdef T_VLT_MATCH_ERROR_1
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import hi::*;
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`elsif T_VLT_MATCH_ERROR_2
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initial $readmemh("", EC_ERROR);
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`elsif T_VLT_MATCH_ERROR_3
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initial #1;
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`endif
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endmodule
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