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58 lines
1.3 KiB
Systemverilog
58 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/);
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int qdel[$];
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int qkept[$];
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task automatic func(ref int vrefed);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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`checkd(vrefed, 2);
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#100;
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vrefed = 10;
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#10;
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`checkd(vrefed, 10);
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endtask
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initial begin
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qkept.push_back(1);
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qkept.push_back(2);
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qkept.push_back(3);
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qdel = qkept;
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$display("qkept=%p qdel=%p", qkept, qdel);
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`checkd(qkept[0], 1);
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`checkd(qkept[1], 2);
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`checkd(qkept[2], 3);
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func(qdel[1]);
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func(qkept[1]);
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$display("qkept=%p qdel=%p", qkept, qdel);
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`checkd(qdel.size, 0);
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`checkd(qkept[0], 1);
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`checkd(qkept[1], 10);
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`checkd(qkept[2], 3);
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end
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initial begin
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#50;
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`checkd(qdel[1], 2);
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`checkd(qkept[1], 2);
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qdel.delete();
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#100;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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