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32 lines
981 B
Systemverilog
32 lines
981 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(input signed [3:0] i4,
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output signed [2:0] ol3,
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output signed [3:0] ol4,
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output signed [4:0] ol5,
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output signed [2:0] or3,
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output signed [3:0] or4,
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output signed [4:0] or5,
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output signed [2:0] os3,
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output signed [3:0] os4,
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output signed [4:0] os5);
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assign ol3 = i4 << 1; // WIDTHTRUNC
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assign ol4 = i4 << 1;
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assign ol5 = i4 << 1; // WIDTHEXPAND, but ok due to shift amount 1
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assign or3 = i4 >> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1?
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assign or4 = i4 >> 1;
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assign or5 = i4 >> 1; // WIDTHEXPAND
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assign os3 = i4 >>> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1?
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assign os4 = i4 >>> 1;
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assign os5 = i4 >>> 1; // WIDTHEXPAND
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endmodule
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