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37 lines
611 B
Systemverilog
37 lines
611 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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parameter P = 1;
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if (P) ;
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if (P)
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begin
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initial $display;
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end
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else
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begin
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initial $display;
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end
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for (genvar v = 0; v < P; ++v) ;
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for (genvar v = 0; v < P; ++v)
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begin
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initial $display;
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end
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case (P)
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1: initial begin end
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2: begin
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initial begin end
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end
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endcase
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endmodule
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