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ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
96 lines
2.1 KiB
Verilog
96 lines
2.1 KiB
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [60:0] p;
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reg [60:0] a;
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reg [20:0] b;
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reg [60:0] shifted;
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always @* begin
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p = a[60:0] ** b[20:0];
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shifted = 2 ** b[20:0];
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end
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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$write("%0x %x %x\n", cyc, p, shifted);
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// Constant versions
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if (61'h1 ** 21'h31 != 61'h1) $stop;
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if (61'h2 ** 21'h10 != 61'h10000) $stop;
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if (61'd10 ** 21'h3 != 61'h3e8) $stop;
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if (61'h3 ** 21'h7 != 61'h88b) $stop;
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if (61'h7ab3811219 ** 21'ha6e30 != 61'h01ea58c703687e81) $stop;
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if (cyc==1) begin
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a <= 61'h0;
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b <= 21'h0;
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end
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if (cyc==2) begin
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a <= 61'h0;
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b <= 21'h3;
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end
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if (cyc==3) begin
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a <= 61'h1;
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b <= 21'h31;
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end
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if (cyc==4) begin
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a <= 61'h2;
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b <= 21'h10;
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end
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if (cyc==5) begin
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a <= 61'd10;
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b <= 21'd3;
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end
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if (cyc==6) begin
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a <= 61'd3;
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b <= 21'd7;
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end
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if (cyc==7) begin
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a <= 61'h7ab3811219;
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b <= 21'ha6e30;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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case (cyc)
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32'd00: ;
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32'd01: ;
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32'd02: ; // 0^x is indeterminate
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32'd03: ; // 0^x is indeterminate
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32'd04: if (p!=61'h1) $stop;
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32'd05: if (p!=61'h10000) $stop;
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32'd06: if (p!=61'h3e8) $stop;
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32'd07: if (p!=61'h88b) $stop;
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32'd08: if (p!=61'h01ea58c703687e81) $stop;
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32'd09: if (p!=61'h01ea58c703687e81) $stop;
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default: $stop;
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endcase
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case (cyc)
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32'd00: ;
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32'd01: ;
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32'd02: if (shifted!=61'h0000000000000001) $stop;
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32'd03: if (shifted!=61'h0000000000000008) $stop;
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32'd04: if (shifted!=61'h0002000000000000) $stop;
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32'd05: if (shifted!=61'h0000000000010000) $stop;
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32'd06: if (shifted!=61'h0000000000000008) $stop;
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32'd07: if (shifted!=61'h0000000000000080) $stop;
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32'd08: if (shifted!=61'h0000000000000000) $stop;
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32'd09: if (shifted!=61'h0000000000000000) $stop;
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default: $stop;
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endcase
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end
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endmodule
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