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7 lines
368 B
Plaintext
7 lines
368 B
Plaintext
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
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[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
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[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
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[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: synthesis full_case, but non-match found
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%Error: t/t_assert_synth.v:40: Verilog $stop
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Aborting...
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