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21 lines
358 B
Systemverilog
21 lines
358 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(
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input wire rst
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);
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integer q;
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always @(*)
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if (rst)
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assign q = 0;
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else
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deassign q;
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endmodule
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