verilator/test_regress/t/t_var_bad_hide2.v
Wilson Snyder 68567e763c Support "package" and $unit.
Add VARHIDDEN warning when signal name hides module name.
2009-11-07 21:05:02 -05:00

11 lines
196 B
Verilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
integer t;
endmodule