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32 lines
653 B
Systemverilog
32 lines
653 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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event e1;
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event e2;
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int v = 0;
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initial begin
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#1 $strobe("v = %0d", v); ->e1;
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@e2 $strobe("v = %0d", v); ->e1;
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@e2 $strobe("v = %0d", v); ->e1;
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@e2 $write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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@e1 v = 1; #1 ->e2;
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@e1 v = 2; #1 ->e2;
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@e1 v = 3; #1 ->e2;
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end
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initial #5 $stop; // timeout
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endmodule
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