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This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
7 lines
366 B
Plaintext
7 lines
366 B
Plaintext
%Warning-NOLATCH: t/t_lint_nolatch_bad.v:11:4: No latches detected in always_latch block
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11 | always_latch
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| ^~~~~~~~~~~~
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... For warning description see https://verilator.org/warn/NOLATCH?v=latest
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... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message.
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%Error: Exiting due to
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