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This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
20 lines
412 B
Systemverilog
20 lines
412 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#2863
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer)
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module test
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(input logic [1:0] a,
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input logic e,
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output logic [1:0] z);
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always_latch
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if (e)
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z[0] = a[0];
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always_latch
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if (e)
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z[1] = a[1];
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endmodule
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