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30 lines
615 B
Systemverilog
30 lines
615 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module x;
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typedef struct {
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int a, b;
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logic [3:0] c;
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} embedded_t;
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typedef struct {
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embedded_t b;
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embedded_t tab [3:0];
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} notembedded_t;
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notembedded_t p;
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embedded_t t [1:0];
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initial begin
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t[1].a = 2;
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p.b.a = 1;
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if (t[1].a != 2) $stop;
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if (p.b.a != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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