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14 lines
391 B
Systemverilog
14 lines
391 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module foo(input logic i_clk); /* verilator public_module */
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endmodule
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// --flatten forces inlining of public module foo.
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module top(input logic i_clk);
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foo f(.*);
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endmodule
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